MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 162

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
162/995
REMAP
PD01_
Res.
31
15
rw
PS_RE
PTP_P
CAN1_REMAP
MAP
30
rw
14
rw
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
[1:0]
Memory map and bit definitions for connectivity line devices:
Bit 31
Bit 30 PTP_PPS_REMAP: Ethernet PTP PPS remapping
Bit 29 TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
Bit 28 SPI3_REMAP: SPI3 remapping
Bit 27
TIM2IT
IREMA
Bit 0 SPI1_REMAP: SPI1 remapping
R1_
29
13
rw
rw
P
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Note: This bit is available only in connectivity line devices and is reserved otherwise.
Note: This bit is available only in connectivity line devices and is reserved otherwise.
REMAP
REMAP
TIM4_
SPI3_
Reserved
This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,
MOSI alternate functions on the GPIO ports.
0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
This bit is set and cleared by software. It enables the Ethernet MAC PPS_PTS to be output
on the PB5 pin.
0: PTP_PPS not output on PB5 pin.
1: PTP_PPS is output on PB5 pin.
This bit is set and cleared by software. It controls the TIM2_ITR1 internal mapping.
0: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
1: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
This bit is set and cleared by software. It controls the mapping of SPI3 NSS, SCK, MISO,
MOSI alternate functions on the GPIO ports.
0: No remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
1: Remap (NSS/PA4, SCK/PC10, MISO/PC11, MOSI/PC12)
Reserved
These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD
access to the Cortex debug port. The default state after reset is SWJ ON without trace. This
allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
28
rw
12
rw
TIM3_REMAP
Res.
27
11
rw
[1:0]
26
10
rw
w
CFG[2:0]
SWJ_
TIM2_REMAP
25
rw
w
9
Doc ID 13902 Rev 9
[1:0]
24
rw
w
8
MII_RMI
I_SEL
TIM1_REMAP
23
rw
rw
7
[1:0]
REMAP
CAN2_
22
rw
rw
6
ETH_R
EMAP
REMAP[1:0]
21
rw
rw
5
USART3_
20
rw
4
REMAP
USART
19
2_
rw
3
Reserved
REMAP
USART
18
1_
rw
2
REMAP
I2C1_
17
rw
1
RM0008
TIM5CH
4_IREM
REMAP
SPI1_
AP
16
rw
rw
0