MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 651

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
24.6.9
15
14
Bits 11:0 CCR[11:0]: Clock control register in Fast/Standard mode (Master mode)
Bits 15:6 Reserved, forced by hardware to 0.
Bits 5:0 TRISE[5:0]: Maximum rise time in Fast/Standard mode (Master mode)
TRISE register (I2C_TRISE)
Address offset: 0x20
Reset value: 0x0002
13
Note: 1. The minimum allowed value is 0x04, except in FAST DUTY mode where the
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
12
Controls the SCL clock in master mode.
Standard mode or SMBus:
T
T
Fast mode:
If DUTY = 0:
T
T
If DUTY = 1: (to reach 400 kHz)
T
T
For instance: in standard mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, T
(0x28 <=> 40d x 125 ns = 5000 ns.)
These bits must be programmed with the maximum SCL rise time given in the I
specification, incremented by 1.
For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and T
therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order
to respect the t
ow
ow
ow
high
high
high
= CCR * T
= 2 * CCR * T
= 16 * CCR * T
minimum allowed value is 0x01
2. t
3. t
4. These timings are without filters.
5. The CCR register must be configured only when the I
6. f
= CCR * T
= CCR * T
= 9 * CCR * T
11
Reserved
high
low
CK
Res.
= a multiple of 10 MHz is required to generate the fast clock at 400 kHz.
includes the SCLH falling edge
includes the SCLH rising edge
10
PCLK1
HIGH
PCLK1
PCLK1
PCLK1
PCLK1
PCLK1
PCLK1
parameter.
9
= 125 ns so CCR must be programmed with 0x28
Doc ID 13902 Rev 9
8
7
6
Inter-integrated circuit (I
rw
5
rw
4
2
C is disabled (PE = 0).
rw
3
TRISE[5:0]
rw
2
PCLK1
2
rw
C) interface
1
2
C bus
= 125 ns
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rw
0