MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 846

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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Table 191. TX interface signal encoding
Table 192. RX interface signal encoding
MII clock sources
To generate both TX_CLK and RX_CLK clock signals, the external PHY must be clocked
with an external 25 MHz as shown in
quartz to provide this clock, the STM32F107xx microcontroller can output this signal on its
MCO pin. In this case, the PLL multiplier has to be configured so as to get the desired
frequency on the MCO pin, from the 25 MHz external quartz.
MII_RX_DV
MII_TX_EN
that follows the final nibble. In order to receive the frame correctly, the MII_RX_DV
signal must encompass the frame, starting no later than the SFD field.
MII_RX_ER: receive error must be asserted for one or more clock periods
(MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere
in the frame. This error condition must be qualified by MII_RX_DV assertion as
described in
0
0
0
0
0
1
1
0
1
MII_RX_ERR
Table
0000 through 1111
0000 through 1111
0
1
1
1
1
0
1
MII_TXD[3:0]
192.
Doc ID 13902 Rev 9
0000 through 1111
0001 through 1101
0000 through 1111
0000 through 1111
MII_RXD[3:0]
Figure
0000
1110
1111
Normal inter-frame
Normal data transmission
289. Instead of using an external 25 MHz
Normal inter-frame
Normal inter-frame
Reserved
False carrier indication
Reserved
Normal data reception
Data reception with errors
Description
Description
RM0008