MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 650

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inter-integrated circuit (I
24.6.8
Note:
650/995
F/S
15
rw
DUTY
1
2
14
rw
Bits 13:12 Reserved, forced by hardware to 0.
Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
F
The CCR register must be configured only when the I2C is disabled (PE = 0).
Bit 15 F/S: I2C master mode selection
Bit 14 DUTY: Fast mode duty cycle
Bit 2 TRA: Transmitter/receiver
Bit 1 BUSY: Bus busy
Bit 0 MSL: Master/slave
PCLK1
13
Reserved
is the multiple of 10 MHz required to generate the Fast clock at 400 kHz.
12
0: Data bytes received
1: Data bytes transmitted
This bit is set depending on the R/W bit of the address byte, at the end of total address
phase.
It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start
condition, loss of bus arbitration (ARLO=1), or when PE=0.
0: No communication on the bus
1: Communication ongoing on the bus
–Set by hardware on detection of SDA or SCL low
–cleared by hardware on detection of a Stop condition.
It indicates a communication in progress on the bus. This information is still updated when
the interface is disabled (PE=0).
0: Slave Mode
1: Master Mode
–Set by hardware as soon as the interface is in Master mode (SB=1).
–Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
0: Standard Mode I2C
1: Fast Mode I2C
0: Fast Mode t
1: Fast Mode t
(ARLO=1), or by hardware when PE=0.
2
C) interface
11
rw
10
rw
low
low
/t
/t
high
high
rw
9
= 2
= 16/9 (see CCR)
Doc ID 13902 Rev 9
rw
8
rw
7
rw
6
CCR[11:0]
rw
5
rw
4
rw
3
rw
2
rw
1
RM0008
rw
0