MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 903

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25
rw rw rw rw rw rw rw
Bits 31:0 RBAP2 / RTSH: Receive buffer 2 address pointer (next descriptor address) / Receive frame
●
Rx DMA descriptors format with IEEE1588 time stamp
Figure 317. Receive descriptor fields format with IEEE1588 time stamp enabled
1. The DMA updates RDES2 and RDES3 with the time stamp value before clearing the OWN bit in RDES0:
RDES2 is updated with the lower 32 time stamp bits (the sub-second field, called RTSL in the
Receive descriptor Word2
field, called RTSH in the
RDES3: Receive descriptor Word3
RDES3 contains the address pointer either to the second data buffer in the descriptor
or to the next descriptor, or it contains time stamp data.
time stamp high
These bits take on two different functions: the application uses them to indicate to the DMA the
location of where to store the data in memory, and then after transferring all the data the DMA
may use these bits to pass back time stamp data.
RBAP1: When the software makes this descriptor available to the DMA (at the moment that the
OWN bit is set to 1 in RDES0), these bits indicate the physical address of buffer 2 when a
descriptor ring structure is used. If the second address chained (RDES1 [24]) bit is set, this address
contains the pointer to the physical memory where the next descriptor is present. If RDES1 [24] is
set, the buffer (next descriptor) address pointer must be bus width-aligned (RDES3[3, 2, or 1:0]
= 0, corresponding to a bus width of 128, 64 or 32. LSBs are ignored internally.) However, when
RDES1 [24] is reset, there are no limitations on the RDES3 value, except for the following condition:
the DMA uses the configured value for its buffer address generation when the RDES3 value is used to
store the start of frame. The DMA ignores RDES3[3, 2, or 1:0] (corresponding to a bus width of 128,
64 or 32) if the address pointer is to a buffer where the middle or last part of the frame is stored.
RTSH: Before it clears the OWN bt in RDES0, the DMA updates this field with the 32 most
significant bits of the time stamp captured for the corresponding receive frame (overwriting the
value for RBAP2). This field has the time stamp only if time stamping is activated and if the Last
segment control bit (LS) in the descriptor is set.
RDES 0
RDES 1
RDES 2
RDES 3
24
rw
CT
RL
31
O
W
N
23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Reserved
Buffer 2 address [31:0] or Next descriptor address [31:0] / Time stamp high[31:0]
[30:29]
Ethernet (ETH): media access control (MAC) with DMA controller
RDES3: Receive descriptor Word3
section) and RDES3 is updated with the upper 32 time stamp bits (the Seconds
Buffer 2 byte count
Buffer 1 address [31:0] / Time stamp low [31:0]
Doc ID 13902 Rev 9
[28:16]
RBP2 / RTSH
Status [30:0]
[15:14]
CTRL
section).
Res.
9
Buffer 1 byte count
8
(1)
7
[12:0]
6
5
4
(1)
RDES2:
3
ai15645
0
2
903/995
1
0