MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 660

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal synchronous asynchronous receiver transmitter (USART)
Note:
Note:
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When a transmission is taking place, a write instruction to the USART_DR register stores
the data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the USART_DR register places
the data directly in the shift register, the data transmission starts, and the TXE bit is
immediately set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data into the USART_DR register, it is mandatory to wait for TC=1
before disabling the USART or causing the microcontroller to enter the low power mode (see
Figure 241: TC/TXE behavior when
Clearing the TC bit is performed by the following software sequence:
1.
2.
Figure 241. TC/TXE behavior when transmitting
1. This example assumes that several other transmissions occured since TE was set. Otherwise, if
The TC bit can also be cleared by writing a ‘0’ to it. This clearing sequence is recommended
only for Multibuffer communication.
Break characters
Setting the SBK bit transmits a break character. The break frame length depends on the M
bit (see
If the SBK bit is set to ‘1’ a break character is sent on the TX line after completing the current
character transmission. This bit is reset by hardware when the break character is completed
(during the stop bit of the break character). The USART inserts a logic 1 bit at the end of the
last break frame to guarantee the recognition of the start bit of the next frame.
If the software resets the SBK bit before the commencement of break transmission, the
break character will not be transmitted. For two consecutive breaks, the SBK bit should be
set after the stop bit of the previous break.
software waits until TXE=1
and writes F1 into
USART_DR
and writes F2 into
USART_DR
software waits until TXE=1
USART_DR had been written for the first time, an IDLE preamble would have been transmitted first.
flag TC
flag TXE
USART_DR
TX LINE
A read from the USART_SR register
A write to the USART_DR register
Figure
239).
software waits until TXE=1
and writes F3 into
USART_DR
set by hardware
cleared by software
Frame 1
F2
TC is not set because
Doc ID 13902 Rev 9
TXE=0
transmitting).
software waits until TXE=1
and writes F3 into
USART_DR
set by hardware
cleared by software
Frame 2
F3
TC is not set because
TXE=0
set by hardware
Frame 3
software wait
TC is set because
until TC=1
TXE=1
RM0008
set by
hardware
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