MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 931

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:0 TSA: Time stamp addend
Bits 31:0 TTSH: Target time stamp high
Ethernet PTP time stamp addend register (ETH_PTPTSAR)
Address offset: 0x0718
Reset value: 0x0000 0000
This register is used by the software to readjust the clock frequency linearly to match the
master clock frequency. This register value is used only when the system time is configured
for Fine update mode (TSFCU bit in ETH_PTPTSCR). This register content is added to a
32-bit accumulator in every clock cycle and the system time is updated whenever the
accumulator overflows.
Ethernet PTP target time high register (ETH_PTPTTHR)
Address offset: 0x071C
Reset value: 0x0000 0000
This register contains the higher 32 bits of time to be compared with the system time for
interrupt event generation. The Target time high register, along with Target time low register,
is used to schedule an interrupt event (TSARU bit in ETH_PTPTSCR) when the system time
exceeds the value programmed in these registers.
This register indicates the 32-bit time value to be added to the Accumulator register to achieve
time synchronization.
This register stores the time in seconds. When the time stamp value matches or exceeds both
Target time stamp registers, the MAC, if enabled, generates an interrupt.
Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 9
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