MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 944

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Reserved
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Bits 31:29 Reserved
Bits 27:17 MFA: Missed frames by the application
Bits 15:0 MFC: Missed frames by the controller
rc_
Bits 31:0 HTDAP: Host transmit descriptor address pointer
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Bit 28 OFOC: Overflow bit for FIFO overflow counter
Bit 16 OMFC: Overflow bit for missed frame counter
Ethernet DMA missed frame and buffer overflow counter register
(ETH_DMAMFBOCR)
Address offset: 0x1020
Reset value: 0x0000 0000
The DMA maintains two counters to track the number of missed frames during reception.
This register reports the current value of the counter. The counter is used for diagnostic
purposes. Bits [15:0] indicate missed frames due to the STM32F107xx buffer being
unavailable (no receive descriptor was available). Bits [27:17] indicate missed frames due to
Rx FIFO overflow conditions and runt frames (good frames of less than 64 bytes).
Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)
Address offset: 0x1048
Reset value: 0x0000 0000
The Current host transmit descriptor register points to the start address of the current
transmit descriptor read by the DMA.
rc_
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r
rc_
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Indicates the number of frames missed by the application
Indicates the number of frames missed by the Controller due to the host receive buffer being
unavailable. This counter is incremented each time the DMA discards an incoming frame.
Cleared on reset. Pointer updated by DMA during operation.
rc_
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rc_
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rc_
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rc_
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rc_
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rc_
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rc_
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rc_
Doc ID 13902 Rev 9
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r
rc_
r
r
rc_
HTDAP
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r
rc_
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r
rc_
r
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rc_
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r
rc_
r
r
rc_
r
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rc_
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rc_
9
9
r
r
rc_
8
8
r
r
MFC
rc_
7
7
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r
rc_
6
6
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r
rc_
5
5
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rc_
4
4
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rc_
3
3
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rc_
RM0008
2
2
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rc_
1
1
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rc_
0
0
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