MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 589

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
23.3
23.3.1
SPI functional description
General description
The block diagram of the SPI is shown in
Figure 207. SPI block diagram
Usually, the SPI is connected to external devices through 4 pins:
●
●
●
●
A basic example of interconnections between a single master and a single slave is
illustrated in
MOSI
MISO
SCK
NSS
MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode
and receive data in master mode.
MOSI: Master Out / Slave In data. This pin can be used to transmit data in master
mode and receive data in slave mode.
SCK: Serial Clock output for SPI masters and input for SPI slaves.
NSS: Slave select. This is an optional pin to select master/ slave mode. This pin acts as
a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid
contention on the data lines. Slave NSS inputs can be driven by standard I/O ports on
the master Device. The NSS pin may also be used as an output if enabled (SSOE bit)
and driven low if the SPI is in master configuration. In this manner, all NSS pins from
devices connected to the Master NSS pin see a low level and become slaves when
they are configured in NSS hardware mode.
Figure
208.
Shift register
Rx buffer
Tx buffer
Master control logic
Baud rate generator
Read
Write
Doc ID 13902 Rev 9
Address and data bus
LSB first
Figure
BR[2:0]
FIRST
LSB
207.
MODE
BIDI
SPI_SR
SPI_CR2
TXE
BSY
IE
SPE BR2
BIDI
OE
RXNE
OVR
IE
Communication
Serial peripheral interface (SPI)
CRC
EN
MOD
ERR
control
IE
F
SPI_CR1
BR1 BR0
CRC
Next
CRC
ERR
0
DFF
0
0
MSTR CPOL CPHA
RX
ONLY
SSOE
0
SSM SSI
TXDM
AEN
TXE
1
0
RXDM
RXNE
AEN
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