MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 202

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Analog-to-digital converter (ADC)
Note:
11.3.4
11.3.5
11.3.6
202/995
Temperature sensor/V
The Temperature sensor is connected to channel ADCx_IN16 and the internal reference
voltage V
and converted as injected or regular channels.
The sensor and V
Single conversion mode
In Single conversion mode the ADC does one conversion. This mode is started either by
setting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external
trigger (for a regular or injected channel), while the CONT bit is 0.
Once the conversion of the selected channel is complete:
The ADC is then stopped.
Continuous conversion mode
In continuous conversion mode ADC starts another conversion as soon as it finishes one.
This mode is started either by external trigger or by setting the ADON bit in the ADC_CR2
register, while the CONT bit is 1.
After each conversion:
Timing diagram
As shown in
converting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC
flag is set and the 16-bit ADC Data register contains the result of the conversion.
If a regular channel was converted:
If an injected channel was converted:
If a regular channel was converted:
If an injected channel was converted:
REFINT
The converted data is stored in the 16-bit ADC_DR register
The EOC (End Of Conversion) flag is set
and an interrupt is generated if the EOCIE is set.
The converted data is stored in the 16-bit ADC_DRJ1 register
The JEOC (End Of Conversion Injected) flag is set
and an interrupt is generated if the JEOCIE bit is set.
The converted data is stored in the 16-bit ADC_DR register
The EOC (End Of Conversion) flag is set
An interrupt is generated if the EOCIE is set.
The converted data is stored in the 16-bit ADC_DRJ1 register
The JEOC (End Of Conversion Injected) flag is set
An interrupt is generated if the JEOCIE bit is set.
Figure
is connected to ADCx_IN17. These two internal channels can be selected
REFINT
26, the ADC needs a stabilization time of t
are only available on the master ADC1 peripheral.
REFINT
Doc ID 13902 Rev 9
internal channels
STAB
before it starts
RM0008

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