MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 293

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
13.3.20
13.3.21
2.
3.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 98. Control circuit in external clock mode 2 + trigger mode
Timer synchronization
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 14.3.15: Timer synchronization on page 349
Debug mode
When the microcontroller enters debug mode (Cortex-M3 core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to
watchdog, bxCAN and I
Configure the channel 1 as follows, to detect rising edges on TI:
–
–
–
–
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
Counter clock = CK_CNT = CK_PSC
IC1F=0000: no filter.
The capture prescaler is not used for triggering and does not need to be
configured.
CC1S=01in TIMx_CCMR1 register to select only the input capture source
CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge
only).
CEN/CNT_EN
Counter register
2
C.
ETR
TIF
Doc ID 13902 Rev 9
TI1
Section 29.16.2: Debug support for timers,
34
Advanced-control timers (TIM1&TIM8)
for details.
35
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