MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 373

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
14.4.18
14.4.19
Table 78.
Offset
0x0C
0x00
0x04
0x08
0x10
0x14
0x18
15
rw
Output Compare
TIMx_CCMR1
TIMx_CCMR1
Input Capture
14
TIMx_SMCR
rw
Reset value
Reset value
Reset value
TIMx_DIER
Reset value
Reset value
Reset value
Reset value
Reset value
Register
TIMx_EGR
TIMx_CR1
TIMx_CR2
TIMx_SR
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
mode
mode
TIMx DMA address for full transfer (TIMx_DMAR)
Address offset: 0x4C
Reset value: 0x0000
TIMx register map
TIMx registers are mapped as 16-bit addressable registers as described in the table below:
TIMx register map and reset values
13
rw
A read or write access to the DMAR register accesses the register located at the address:
“(TIMx_CR1 address) + DBA + (DMA index)” in which:
TIMx_CR1 address is the address of the control register 1,
DBA is the DMA base address configured in the TIMx_DCR register,
DMA index is the offset automatically controlled by the DMA transfer, depending on the
length of the transfer DBL in the TIMx_DCR register.
12
rw
11
rw
10
rw
Reserved
Reserved
Reserved
Reserved
rw
9
Reserved
Doc ID 13902 Rev 9
Reserved
DMAB[15:0]
rw
8
Reserved
Reserved
rw
7
rw
6
0
0
0
IC2F[3:0]
0
0
0
0
OC2M
[2:0]
rw
5
ETPS
0
0
0
0
[1:0]
0
0
0
0
0
General-purpose timer (TIMx)
0
0
0
0
0
PSC
[1:0]
rw
IC2
4
ETF[3:0]
0
0
0
0
0
CC2S
CC2S
CKD
0
0
0
0
0
0
[1:0]
[1:0]
[1:0]
rw
3
0
0
0
0
0
0
0
0
0
0
IC1F[3:0]
MMS[2:0]
CMS
0
0
0
0
0
0
0
0
rw
[1:0]
2
TS[2:0]
OC1M
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
rw
1
0
0
0
0
0
0
0
PSC
[1:0]
IC1
373/995
Reserved
SMS[2:0]
0
0
0
0
0
0
0
CC1S
CC1S
rw
0
0
0
0
0
0
0
[1:0]
[1:0]
0
0
0
0
0
0
0
0