MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 910

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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Bits 31:0 HTH: Hash table high
Ethernet MAC hash table high register (ETH_MACHTHR)
Address offset: 0x0008
Reset value: 0x0000 0000
The 64-bit Hash table is used for group address filtering. For hash filtering, the contents of
the destination address in the incoming frame are passed through the CRC logic, and the
upper 6 bits in the CRC register are used to index the contents of the Hash table. The most
significant bit determines the register to be used (hash table high/hash table low), and the
other 5 bits determine which bit within the register. A hash value of 0b0 0000 selects bit 0 in
the selected register, and a value of 0b1 1111 selects bit 31 in the selected register.
For example, if the DA of the incoming frame is received as 0x1F52 419C B6AF (0x1F is the
first byte received on the MII interface), then the internally calculated 6-bit Hash value is
0x2C and the HTH register bit[12] is checked for filtering. If the DA of the incoming frame is
received as 0xA00A 9800 0045, then the calculated 6-bit Hash value is 0x07 and the HTL
register bit[7] is checked for filtering.
If the corresponding bit value in the register is 1, the frame is accepted. Otherwise, it is
rejected. If the PAM (pass all multicast) bit is set in the ETH_MACFFR register, then all
multicast frames are accepted regardless of the multicast hash values.
The Hash table high register contains the higher 32 bits of the multicast Hash table.
Bit 3 DAIF: Destination address inverse filtering
Bit 2 HM: Hash multicast
Bit 1 HU: Hash unicast
Bit 0 PM: Promiscuous mode
This field contains the upper 32 bits of Hash table.
When this bit is set, the address check block operates in inverse filtering mode for the DA
address comparison for both unicast and multicast frames.
When reset, normal filtering of frames is performed.
When set, MAC performs destination address filtering of received multicast frames according
to the hash table.
When reset, the MAC performs a perfect destination address filtering for multicast frames, that
is, it compares the DA field with the values programmed in DA registers.
When set, MAC performs destination address filtering of unicast frames according to the hash
table.
When reset, the MAC performs a perfect destination address filtering for unicast frames, that
is, it compares the DA field with the values programmed in DA registers.
When this bit is set, the address filters pass all incoming frames regardless of their destination
or source address. The SA/DA filter fails status bits in the receive status word are always
cleared when PM is set.
Doc ID 13902 Rev 9
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