MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 359

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bits 6:4 TS: Trigger selection
Bits 2:0 SMS: Slave mode selection
Table 76.
1. When a timer is not present in the product, the corresponding trigger ITRx is not available.
Bit 3 Reserved, always read as 0.
Slave TIM
TIM2
TIM3
TIM4
TIM5
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0). TIM1
001: Internal Trigger 1 (ITR1). TIM2
010: Internal Trigger 2 (ITR2). TIM3
011: Internal Trigger 3 (ITR3). TIM4
100: TI1 Edge Detector (TI1F_ED).
101: Filtered Timer Input 1 (TI1FP1).
110: Filtered Timer Input 2 (TI2FP2).
111: External Trigger input (ETRF).
See
meaning for each Timer.
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Table 76: TIMx Internal trigger connection on page 359
TIMx Internal trigger connection
avoid wrong edge detections at the transition.
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
ITR0 (TS = 000)
TIM1
TIM1
TIM1
TIM2
Doc ID 13902 Rev 9
ITR1 (TS = 001)
TIM8
TIM2
TIM2
TIM3
(1)
ITR2 (TS = 010)
General-purpose timer (TIMx)
TIM3
TIM5
TIM3
TIM4
for more details on ITRx
ITR3 (TS = 011)
TIM4
TIM4
TIM8
TIM8
359/995