MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 954

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug support (DBG)
29.2
29.3
29.3.1
954/995
Reference ARM documentation
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SWJ debug port (serial wire and JTAG)
The STM32F10xxx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an
ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-
DP (2-pin) interface.
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In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
Figure 321. SWJ debug port
Figure 321
TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP.
Mechanism to select the JTAG-DP or the SW-DP
By default, the JTAG-Debug Port is active.
If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG
sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the
JTCK/SWCLK
JTMS/SWDIO
Cortex™-M3 r1p1 Technical Reference Manual (TRM) (see
page
ARM Debug Interface V5
ARM CoreSight Design Kit revision r1p1 Technical Reference Manual
The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port.
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
JNTRST
JTDO
1)
JTDI
shows that the asynchronous TRACE output (TRACESWO) is multiplexed with
TRACESWO
SWDITMS
SWDO
TDO
TDI
nTRST
SWDOEN
SWCLKTCK
SWJ-DP
SWD/JTAG
(asynchronous trace)
Doc ID 13902 Rev 9
select
nTRST
DBGDOEN
TDI
TCK
DBGDO
DBGCLK
TMS
DBGDI
TDO
JTAG-DP
SW-DP
Related documents on
DBGRESETn
nPOTRST
nPOTRST
From
power-on
reset
RM0008