MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 889

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25
Reserved
rw rw rw rw
Bits 6:3 CC: Collision count
31:29 Reserved
Bit 11 LCA: Loss of carrier
Bit 10 NC: No carrier
●
Bit 9 LCO: Late collision
Bit 8 EC: Excessive collision
Bit 7 VF: VLAN frame
Bit 2 ED: Excessive deferral
Bit 1 UF: Underflow error
Bit 0 DB: Deferred bit
TDES1: Transmit descriptor Word1
When set, this bit indicates that a loss of carrier occurred during frame transmission (that is,
the MII_CRS signal was inactive for one or more transmit clock periods during frame
transmission). This is valid only for the frames transmitted without collision when the MAC
operates in Half-duplex mode.
When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted
during transmission.
When set, this bit indicates that frame transmission was aborted due to a collision occurring
after the collision window (64 byte times, including preamble, in MII mode). This bit is not valid
if the Underflow Error bit is set.
When set, this bit indicates that the transmission was aborted after 16 successive collisions
while attempting to transmit the current frame. If the RD (Disable retry) bit in the MAC
Configuration register is set, this bit is set after the first collision, and the transmission of the
frame is aborted.
When set, this bit indicates that the transmitted frame was a VLAN-type frame.
This 4-bit counter value indicates the number of collisions occurring before the frame was
transmitted. The count is not valid when the Excessive collisions bit (TDES0[8]) is set.
When set, this bit indicates that the transmission has ended because of excessive deferral of
over 24 288 bit times if the Deferral check (DC) bit in the MAC Control register is set high.
When set, this bit indicates that the MAC aborted the frame because data arrived late from the
RAM memory. Underflow error indicates that the DMA encountered an empty transmit buffer
while transmitting the frame. The transmission process enters the Suspended state and sets
both Transmit underflow (Register 5[5]) and Transmit interrupt (Register 5[0]).
When set, this bit indicates that the MAC defers before transmission because of the presence
of the carrier. This bit is valid only in Half-duplex mode.
24
rw
23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw
TBS2
Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 9
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw rw
9
8
7
TBS1
6
5
4
3
2
889/995
1
0