MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 844

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
27.4.2
844/995
Figure 287. MDIO timing and frame structure - Read cycle
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock
whose source is the application clock (AHB clock). The divide factor depends on the clock
range setting in the MII Address register.
Table 190
Table 190. Clock range
Media-independent interface: MII
The media-independent interface (MII) defines the interconnection between the MAC
sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.
0100, 0101, 0110, 0111
MDIO
MDC
Selection
shows how to set the clock ranges.
Preamble
0000
0001
0010
0011
32 1's
Start
of
frame
0 1 1
OP
code
0
Data to PHY
Doc ID 13902 Rev 9
A4 A3 A2 A1 A0 R4 R3
PHY address
AHB clock
60-72 MHz
20-35 MHz
35-60 MHz
Reserved
Reserved
Register address Turn
R2 R1 R0
around
D15 D14
Data from PHY
AHB clock / 42
AHB clock / 16
AHB clock / 26
MDC clock
data
-
-
D1 D0
RM0008
ai15627