MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 110

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Connectivity line devices: reset and clock control (RCC)
7.2.3
7.2.4
110/995
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the
register
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the
The HSIRDY flag in the
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the
(RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to
PLLs
The main PLL provides a frequency multiplier starting from one of the following clock
sources:
●
●
Refer to
PLL2 and PLL3 are clocked by HSE through a specific configurable divider. Refer to
Figure 11
The configuration of each PLL (selection of clock source, predivision factor and
multiplication factor) must be done before enabling the PLL. Each PLL should be enabled
after its input clock becomes stable (ready flag). Once the PLL is enabled, these parameters
can not be changed.
When changing the entry clock source of the main PLL, the original clock source must be
switched off only after the selection of the new clock source (done through bit PLLSRC in
the Clock configuration register (RCC_CFGR)).
An interrupt can be generated when the PLL is ready if enabled in the
register
LSE clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in
register
The LSERDY flag in the
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the
register
HSI clock divided by 2
HSE or PLL2 clock through a configurable divider
(RCC_CR).
(RCC_CIR).
(RCC_BDCR).
(RCC_CIR).
Figure 11
and Clock configuration register2 (RCC_CFGR2)
Clock control register
and
Clock control register
Section 7.2.7: Clock security system (CSS) on page
Clock control register (RCC_CR)
Backup domain control register (RCC_BDCR)
Doc ID 13902 Rev 9
(RCC_CR).
(RCC_CR).
indicates if the HSI RC is stable or
Backup domain control
Clock control register
Clock interrupt
indicates if the LSE
Clock interrupt
112.
Clock control
A
= 25 °C.
RM0008