MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 586

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial peripheral interface (SPI)
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Serial peripheral interface (SPI)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
SPI introduction
In high-density and connectivity line devices, the SPI interface gives the flexibility to get
either the SPI protocol or the I
selected. It is possible to switch the interface from SPI to I
In low- and medium-density devices, the I
The serial peripheral interface (SPI) allows half/ full-duplex, synchronous, serial
communication with external devices. The interface can be configured as the master and in
this case it provides the communication clock (SCK) to the external slave device. The
interface is also capable of operating in multimaster configuration.
It may be used for a variety of purposes, including Simplex synchronous transfers on two
lines with a possible bidirectional data line or reliable communication using CRC checking.
I
address four different audio standards including the I
LSB-justified standards and the PCM standard. It can operate in slave or master mode with
half-duplex communication. Master clock may be provided by the interface to an external
slave component when the I
2
S is also a synchronous, serial communication interface with a 3-pin protocol. It can
Warning:
Since some SPI3/I2S3 pins are shared with JTAG pins
(SPI3_NSS/I2S3_WS with JTDI and SPI3_SCK/I2S3_CK with
JTDO), they are not controlled by the I/O controller and are
reserved for JTAG usage (after each Reset).
For this purpose prior to configure the SPI3/I2S3 pins, the
user has to disable the JTAG and use the SWD interface
(when debugging the application), or disable both JTAG/SWD
interfaces (for standalone application). For more information
on the configuration of JTAG/SWD interface pins, please refer
to
Section 8.3.5: JTAG/SWD alternate function
2
S is configured as the communication master.
2
Doc ID 13902 Rev 9
S audio protocol. By default, it is the SPI function that is
2
S protocol is not available.
2
S Phillips standard, the MSB- and
2
S by software.
remapping.
RM0008