MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 314

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced-control timers (TIM1&TIM8)
13.4.17
13.4.18
Note:
314/995
MOE
15
15
rw
rw
AOE
14
14
rw
rw
Bits 15:0 CCR4[15:0]: Capture/Compare value
Bit 15 MOE: Main output enable
Bit 14 AOE: Automatic output enable
TIM1&TIM8 capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000
TIM1&TIM8 break and dead-time register (TIMx_BDTR)
Address offset: 0x44
Reset value: 0x0000
As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
BKP
13
rw
13
rw
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit
OC4PE). Else the preload value is copied in the active capture/compare 4 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (IC4).
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register).
See OC/OCN enable description for more details
capture/compare enable register (TIMx_CCER) on page
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
BKE
12
rw
12
rw
in TIMx_BDTR register).
OSSR
11
11
rw
rw
OSSI
10
rw
10
rw
rw
rw
9
9
LOCK[1:0]
Doc ID 13902 Rev 9
CCR4[15:0]
rw
rw
8
8
rw
rw
7
7
rw
rw
6
6
(Section 13.4.9: TIM1&TIM8
rw
rw
5
5
308).
rw
rw
4
4
DTG[7:0]
rw
rw
3
3
rw
rw
2
2
rw
rw
1
1
RM0008
rw
rw
0
0