MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 890

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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31 30 29 28 27 26 25
31 30 29 28 27 26 25
Bits 31:0 TBAP1 / TTSL: Transmit buffer 1 address pointer / Transmit frame time stamp low
28:16 TBS2: Transmit buffer 2 size
15:13 Reserved
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●
12:0 TBS1: Transmit buffer 1 size
TDES2: Transmit descriptor Word2
TDES2 contains the address pointer to the first buffer of the descriptor or it contains
time stamp data.
TDES3: Transmit descriptor Word3
TDES3 contains the address pointer either to the second buffer of the descriptor or the
next descriptor, or it contains time stamp data.
These bits take on two different functions: the application uses them to indicate to the DMA the
location of data in memory. And then after transferring all these data, the DMA may then use
these bits to pass back time stamp data.
TBAP: When the software makes this descriptor available to the DMA (at the moment that the
OWN bit is set to 1 in TDES0), these bits indicate the physical address of Buffer 1. There is no
limitation on the buffer address alignment. See
details on buffer address alignment.
TTSL: Before it clears the OWN bt in TDES0, the DMA updates this field with the 32 least
significant bits of the time stamp captured for the corresponding transmit frame (overwriting the
value for TBAP1). This field has the time stamp only if time stamping is activated for this frame
(see TTSE, TDES0 bit 25) and if the Last segment control bit (LS) in the descriptor is set.
These bits indicate the second data buffer size in bytes. This field is not valid if TDES0[20] is
set.
These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this
buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]).
24
24
23 22 21 20 19 18 17 16 15 14 13 12 11 10
23 22 21 20 19 18 17 16 15 14 13 12 11 10
Doc ID 13902 Rev 9
TBAP2/TTSH
TBAP1/TTSL
rw
rw
Host data buffer alignment on page 880
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for further
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RM0008
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