MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 561

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
RM0008
Figure 206. Event flags and interrupt generation
CAN_TSR
CAN_RF0R
CAN_RF1R
CAN_ESR
CAN_MSR
The transmit interrupt can be generated by the following events:
The FIFO 0 interrupt can be generated by the following events:
The FIFO 1 interrupt can be generated by the following events:
Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set.
Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set.
Transmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set.
Reception of a new message, FMP0 bits in the CAN_RF0R register are not ‘00’.
FIFO0 full condition, FULL0 bit in the CAN_RF0R register set.
FIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set.
Reception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’.
FIFO1 full condition, FULL1 bit in the CAN_RF1R register set.
FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.
1LEC6
FULL0
FULL1
SLAKI
FOVR0
FMP0
FMP1
FOVR1
WKUI
RQCP0
RQCP1
RQCP2
EWGF
EPVF
BOFF
+
CAN_IER
EWGIE
FMPIE0
FMPIE1
WKUIE
FOVIE0
ERRIE
FFIE1
FOVIE1
BOFIE
FFIE0
EPVIE
Doc ID 13902 Rev 9
TMEIE
LECIE
SLKIE
&
&
&
&
&
&
&
&
&
&
&
+
+
+
INTERRUPT
CAN_MSR
INTERRUPT
INTERRUPT
TRANSMIT
ERRI
FIFO 0
FIFO 1
Controller area network (bxCAN)
&
&
&
+
STATUS CHANGE
INTERRUPT
ERROR
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