MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 77

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Figure 8.
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
2. For full details about the internal and external clock source characteristics, please refer to the “Electrical
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2.
The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
OSC32_OUT
OSC32_IN
OSC_OUT
64 MHz.
characteristics” section in your device datasheet.
OSC_IN
MCO
Clock tree
4-16 MHz
32.768 kHz
Main
Clock Output
HSE OSC
LSE OSC
HSI RC
8 MHz
LSI RC
40 kHz
PLLSRC
MCO
x2, x3, x4
PLLMUL
HSI
..., x16
Low-, medium- and high-density reset and clock control (RCC)
PLLXTPRE
PLL
/2
/128
LSE
/2
LSI
RTCSEL[1:0]
/2
HSE
Doc ID 13902 Rev 9
SYSCLK
PLLCLK
HSI
PLLCLK
RTCCLK
to Independent Watchdog (IWDG)
HSI
HSE
CSS
SW
SYSCLK
72 MHz
to RTC
max
IWDGCLK
Prescaler
/1, 2..512
AHB
Prescaler
Peripheral clock
enable
Peripheral clock
enable
/1, 1.5
USB
/1, 2, 4, 8, 16
If (APB1 prescaler =1) x1
/1, 2, 4, 8, 16
TIM2,3,4,5,6,7
If (APB2 prescaler =1) x1
TIM1 & 8 timers
Peripheral clock
enable
Peripheral clock
enable
/8
Prescaler
Prescaler
72 MHz max
APB2
APB1
Prescaler
/2, 4, 6, 8
Clock
Enable
/2
ADC
48 MHz
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low -speed external clock signal
Legend:
I2S3CLK
I2S2CLK
Peripheral clock
enable
else x2
72 MHz max
else x2
36 MHz max
ADCCLK 14 MHz max
Peripheral Clock
Enable
Peripheral Clock
Enable
USBCLK
to USB interface
Peripheral Clock
Enable
HCLK
to AHB bus, core,
memory and DMA
FCLK Cortex
free running clock
to I2S3
to I2S2
to Cortex System timer
Peripheral Clock
Enable
To SDIO AHB interface
FSMCCLK
SDIOCLK
HCLK/2
to TIM2,3,4,5,6 and 7
TIMxCLK
TIMXCLK
peripherals to APB2
PCLK1
PCLK2
to APB1
peripherals
to ADC1, 2 or 3
to FSMC
to TIM1 and TIM8
to SDIO
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