MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 295

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
13.4.2
Res.
15
OIS4
14
rw
Bit 15 Reserved, always read as 0
Bit 14 OIS4: Output Idle state 4 (OC4 output)
Bit 13 OIS3N: Output Idle state 3 (OC3N output)
Bit 12 OIS3: Output Idle state 3 (OC3 output)
Bit 11 OIS2N: Output Idle state 2 (OC2N output)
Bit 10 OIS2: Output Idle state 2 (OC2 output)
TIM1&TIM8 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
OIS3N
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
13
rw
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
OIS3
refer to OIS1 bit
refer to OIS1N bit
refer to OIS1 bit
refer to OIS1N bit
refer to OIS1 bit
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
–Counter overflow/underflow
–Setting the UG bit
–Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
–Counter overflow/underflow
–Setting the UG bit
–Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
12
rw
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
OIS2N
11
rw
OIS2
10
rw
OIS1N
rw
9
Doc ID 13902 Rev 9
OIS1
rw
8
TI1S
rw
7
rw
6
Advanced-control timers (TIM1&TIM8)
MMS[2:0]
rw
5
rw
4
CCDS
rw
3
CCUS
rw
2
Res.
1
295/995
CCPC
rw
0