MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 408

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Window watchdog (WWDG)
18.6.3
18.6.4
Table 83.
408/995
Offset
31
15
0x00
0x04
0x08
30
14
WWDG_CFR
WWDG_CR
Reset value
Reset value
WWDG_SR
Reset value
Register
Bits 8:7 WDGTB[1:0]: Timer base
Bits 6:0 W[6:0]: 7-bit window value
Bit 31:1Reserved
Status register (WWDG_SR)
Address offset: 0x08
Reset value: 0x00
WWDG register map
The following table gives the WWDG register map and reset values.
WWDG register map and reset values
Refer to
Bit 0 EWIF: Early wakeup interrupt flag
29
13
The time base of the prescaler can be modified as follows:
00: CK Counter Clock (PCLK1 div 4096) div 1
01: CK Counter Clock (PCLK1 div 4096) div 2
10: CK Counter Clock (PCLK1 div 4096) div 4
11: CK Counter Clock (PCLK1 div 4096) div 8
These bits contain the window value to be compared to the downcounter.
28
12
This bit is set by hardware when the counter has reached the value 40h. It must be cleared
by software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not
enabled.
Table 1 on page 41
27
11
26
10
25
9
for the register boundary addresses.
Doc ID 13902 Rev 9
Reserved
Reserved
24
8
Reserved
Reserved
23
7
Reserved
22
6
21
5
20
4
0
19
3
0
0
0
1
1
18
2
1
1
1
1
W[6:0]
T[6:0]
17
1
1
1
RM0008
1
1
rc_w0
EWIF
1
1
16
0
1
1
0

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