MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 988

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision history
988/995
Table 215. Document revision history (continued)
26-Sep-2008
Date
Revision
6
This reference manual also applies to low-density STM32F101xx,
STM32F102xx and STM32F103xx devices, and to medium-density
STM32F102xx devices. In all sections, definitions of low-density and
medium-density devices updated.
Section 1.3: Peripheral availability on page 37
Section 2.3.3: Embedded Flash memory on page 44
Battery backup domain on page 54
register (GPIOx_IDR) (x=A..G) on page 149
Section 8.4: AFIO registers on page
description in
Section 13.2: TIM1&TIM8 main features on page 253
TIMx main features on page 320
synchronization on page
FSMC_CLK signal direction corrected in
page
General timing rules on page
In
value modified, WAITEN bit default value after reset is 1, bits [5:6] definition
modified, , FACCEN default value after reset specified. NWE signal behavior
corrected in
(CRAM) on page
and OneNAND devices, and it does not support the asynchronous wait
feature. SRAM and ROM 32 memory data size removed from
Flash/PSRAM supported memories and transactions on page
Data latency versus NOR Flash latency on page 431
bits are reserved in
(FSMC_BWTR1..4) on page
Section 19.6.3: Timing diagrams for NAND, ATA and PC Card on page 444
modified.Definition of PWID bits modified in
Card controller registers on page
computation ECC (NAND Flash) on page 447
Interrupt Mapper definition modified in
blocks on page
Section 21.5: USB registers on page
Section 24.3.8: Packet error checking on page 639
Section : Start bit detection on page 661
in
“RAM size register” section removed from
signature on page
register 2..4 (FSMC_SR2..4) on page
Small text changes.
Status register (USART_SR) on page
Section 19.5.6: NOR/PSRAM controller registers on page
410. “Feedback clock” paragraph removed from
Doc ID 13902 Rev 9
Figure 174: Synchronous multiplexed write mode - PSRAM
Section 9.3.6: Pending register (EXTI_PR) on page
514. USB register and memory base addresses modified in
434. The FSMC interface does not support COSMO RAM
949. Bit definitions updated in
SRAM/NOR-Flash write timing registers 1..4
349, TS=000.
440.
417.
updated. In
Changes
448.
modified. Reset value of
158. Note removed from bits 18:0
526.
449.
Section 19.6.6: Error correction code
Section 21.3.1: Description of USB
683.
added. PE bit description specified
Figure 19.3: AHB interface on
Section 28: Device electronic
Section 19.6.7: NAND Flash/PC
modified. Note added in
Section 14.3.15: Timer
added.
modified.
FIFO status and interrupt
modified.
updated.
modified. Bits 19:16
and
Section 19.5.3:
Section 14.2:
Port input data
436: reset
Table 92: NOR
Section 4.1.2:
416.
180.
RM0008