MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 431

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Caution:
Data latency versus NOR Flash latency
The data latency is the number of cycles to wait before sampling the data. The DATLAT
value must be consistent with the latency value specified in the NOR Flash configuration
register. The FSMC does not include the clock cycle when NADV is low in the data latency
count.
Some NOR Flash memories include the NADV Low cycle in the data latency count, so the
exact relation between the NOR Flash latency and the FMSC DATLAT parameter can be
either of:
●
●
Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can
be set to its minimum value. As a result, the FSMC samples the data and waits long enough
to evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and
real data are taken.
Other memories do not assert NWAIT during latency. In this case the latency must be set
correctly for both the FSMC and the memory, otherwise invalid data are mistaken for good
data, or valid data are lost in the initial phase of the memory access.
Single-burst transfer
When the selected bank is configured in synchronous burst mode, if an AHB single-burst
transaction is requested, the FSMC performs a burst transaction of length 1 (if the AHB
transfer is 16-bit), or length 2 (if the AHB transfer is 32-bit) and de-assert the chip select
signal when the last data is strobed.
Clearly, such a transfer is not the most efficient in terms of cycles (compared to an
asynchronous read). Nevertheless, a random asynchronous access would first require to re-
program the memory access mode, which would altogether last longer.
Wait management
For synchronous burst NOR Flash, NWAIT is evaluated after the programmed latency
period, (DATALAT+1) CLK clock cycles.
If NWAIT is sensed active (low level when WAITPOL = 0, high level when WAITPOL = 1),
wait states are inserted until NWAIT is sensed inactive (high level when WAITPOL = 0, low
level when WAITPOL = 1).
When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1)
or on the next clock edge (bit WAITCFG = 0).
During wait-state insertion via the NWAIT signal, the controller continues to send clock
pulses to the memory, keeping the chip select and output enable signals valid, and does not
consider the data valid.
There are two timing configurations for the NOR Flash NWAIT signal in burst mode:
●
●
These two NOR Flash wait state configurations are supported by the FSMC, individually for
each chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3).
NOR Flash latency = DATLAT + 2
NOR Flash latency = DATLAT + 3
Flash memory asserts the NWAIT signal one data cycle before the wait state (default
after reset)
Flash memory asserts the NWAIT signal during the wait state
Doc ID 13902 Rev 9
Flexible static memory controller (FSMC)
431/995