MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 447

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
19.6.6
When this functionality is needed, it can be guaranteed by programming the MEMHOLD
value to meet the t
then has the hold delay of (MEMHOLD + 1) HCLK cycles inserted from the rising edge of
the NWE signal to the next access.
To overcome this timing constraint, the attribute memory space can be used by
programming its timing register with an ATTHOLD value that meets the t
leaving the MEMHOLD value at its minimum. Then, the CPU must use the common memory
space for all NAND Flash read and write accesses, except when writing the last address
byte to the NAND Flash device, where the CPU must write to the attribute memory space.
Error correction code computation ECC (NAND Flash)
The FSMC PC-Card controller includes two error correction code computation hardware
blocks, one per memory bank. They are used to reduce the host CPU workload when
processing the error correction code by software in the system.
These two registers are identical and associated with bank 2 and bank 3, respectively. As a
consequence, no hardware ECC computation is available for memories connected to bank
4.
The error correction code (ECC) algorithm implemented in the FSMC can perform 1-bit error
correction and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read
from or written to NAND Flash.
The ECC modules monitor the NAND Flash databus and read/write signals (NCE and NWE)
each time the NAND Flash memory bank is active.
The functional operations are:
●
●
Once the desired number of bytes has been read from/written to the NAND Flash by the
host CPU, the FSMC_ECCR2/3 registers must be read in order to retrieve the computed
value. Once read, they should be cleared by resetting the ECCEN bit to zero. To compute a
new data block, the ECCEN bit must be set to one in the FSMC_PCR2/3 registers.
When access to NAND Flash is made to bank 2 or bank 3, the data present on the
D[15:0] bus is latched and used for ECC computation.
When access to NAND Flash occurs at any other address, the ECC logic is idle, and
does not perform any operation. Thus, write operations for defining commands or
addresses to NAND Flash are not taken into account for ECC computation.
WB
timing, however any CPU read or write access to the NAND Flash
Doc ID 13902 Rev 9
Flexible static memory controller (FSMC)
WB
timing, and
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