MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 382

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Basic timers (TIM6&TIM7)
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Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
Note: Gated mode can work only if the CEN bit has been previously set by software. However
CEN is cleared automatically in one-pulse mode, when an update event occurs.
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
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trigger mode can set the CEN bit automatically by hardware.
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
Doc ID 13902 Rev 9
RM0008