MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 731

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rc_w1
OTG_FS core interrupt register (OTG_FS_GINTSTS)
Address offset: 0x014
Reset value: 0x0400 0020
This register interrupts the application for system-level events in the current mode (Device
mode or Host mode).
Some of the bits in this register are valid only in Host mode, while others are valid in Device
mode only. This register also indicates the current mode. To clear the interrupt status bits of
the rc_w1 type, the application must write 1 into the bit.
The FIFO status interrupts are read-only; once software reads from or writes to the FIFO
while servicing these interrupts, FIFO interrupt conditions are cleared automatically.
The application must clear the OTG_FS_GINTSTS register at initialization before
unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
Bit 31 WKUPINT: Resume/remote wakeup detected interrupt
Bit 30 SRQINT: Session request/new session detected interrupt
Bit 29 DISCINT: Disconnect detected interrupt
Bit 28 CIDSCHG: Connector ID status change
Bit 27 Reserved
Bit 26 PTXFE: Periodic TxFIFO empty
r
In Device mode, this interrupt is asserted when a resume is detected on the USB. In Host
mode, this interrupt is asserted when a remote wakeup is detected on the USB.
Note: Accessible in both Device and Host modes.
In Host mode, this interrupt is asserted when a session request is detected from the device. In
Device mode, this interrupt is asserted when V
device. Accessible in both Device and Host modes.
Asserted when a device disconnect is detected.
Note: Only accessible in Host mode.
The core sets this bit when there is a change in connector ID status.
Note: Accessible in both Device and Host modes.
Asserted when the periodic transmit FIFO is either half or completely empty and there is space
for at least one entry to be written in the periodic request queue. The half or completely empty
status is determined by the periodic TxFIFO empty level bit in the Core AHB configuration
register (PTXFELVL bit in OTG_FS_GAHBCFG).
Note: Only accessible in Host mode.
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Res.
rc_w1
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Doc ID 13902 Rev 9
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rc_w1
BUS
is in the valid range for a B-peripheral
USB on-the-go full-speed (OTG_FS)
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