MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 848

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
27.4.4
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RMII clock sources
As described in the
50 MHz clock signal on its MCO output pin and you then have to configure this output value
through PLL configuration.
Figure 291. RMII clock sources
MII/RMII selection
The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the
AFIO_MAPR register. The application has to set the MII/RMII mode while the Ethernet
controller is under reset or before enabling the clocks.
MII/RMII internal clock scheme
The clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s
operations is described in
Figure 292. Clock scheme
1. The MII/RMII selection is controlled through bit 23, MII_RMII_SEL, in the
RMII_REF_CK as AF
(50 MHz)
(25 MHz or 2.5 MHz)
MII_RX_CLK as AF
(25 MHz or 2.5 MHz)
MII_TX_CLK as AF
25 MHz
RMII clock sources
STM32
GPIO and AF
GPIO and AF
PLL
controller
controller
Figure
MCO
Doc ID 13902 Rev 9
50 MHz
292.
25 MHz or 2.5 MHz
25 MHz or 2.5 MHz
Sync. divider
/2 for 100 Mb/s
/20 for 10 Mb/s
50 MHz
section, the STM32F107xx could provide this
REF_CLK
50 MHz
0 MII
1 RMII
0
1
0
1
For 10/100 Mbit/s
must be greater
than 25 MHz
(1)
or 2.5 MHz
or 2.5 MHz
25 MHz
25 MHz
HCLK
External
AFIO_MAPR
PHY
MACTXCLK
MACRXCLK
HCLK
register.
ai15625
MAC
RMII
TX
RX
RM0008
AHB
ai15650