MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 417

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
19.5.3
19.5.4
Table 92.
General timing rules
Signals synchronization
●
●
NOR Flash/PSRAM controller timing diagrams
Asynchronous static memories (NOR Flash, SRAM)
●
●
●
PSRAM
(muxed I/Os
and nonmuxed
I/Os)
SRAM and
ROM
Device
All controller output signals change on the rising edge of the internal clock (HCLK)
In synchronous write mode (PSRAM devices), the output data changes on the falling
edge of the memory clock (CLK)
Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
The FSMC always samples the data before de-asserting the chip select signal NE. This
guarantees that the memory data-hold timing constraint is met (chip enable high to
data transition, usually 0 ns min.)
When extended mode is set, it is possible to mix modes A, B, C and D in read and write
(it is for instance possible to read in mode A and write in mode B).
NOR Flash/PSRAM supported memories and transactions (continued)
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Mode
Doc ID 13902 Rev 9
R/W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
8 / 16 /
8 / 16 /
16/32
AHB
data
size
16
16
32
32
16
32
32
32
8
8
8
8
-
data size
Memory
Flexible static memory controller (FSMC)
8 / 16
8 / 16
16
16
16
16
16
16
16
16
16
16
16
16
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Allowed/
allowed
not
Split into 2 FSMC
accesses
Split into 2 FSMC
accesses
Mode is not supported
Use of byte lanes NBL[1:0]
Use of byte lanes NBL[1:0]
Use of byte lanes NBL[1:0]
Use of byte lanes NBL[1:0]
Comments
417/995