MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 933

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bits 22:17 RDP: Rx DMA PBL
Bits 15:14 RTPR: Rx Tx priority ratio
Bits 13:8 PBL: Programmable burst length
Bits 6:2 DSL: Descriptor skip length
Bit 16 FB: Fixed burst
Bit 7 Reserved
Bit 1 DA: DMA Arbitration
Bit 0 SR: Software reset
These bits indicate the maximum number of beats to be transferred in one RxDMA transaction.
This is the maximum value that is used in a single block read/write operation. The RxDMA
always attempts to burst as specified in RDP each time it starts a burst transfer on the host
bus. RDP can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value
results in undefined behavior.
These bits are valid and applicable only when USP is set high.
This bit controls whether the AHB Master interface performs fixed burst transfers or not. When
set, the AHB uses only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst
transfers. When reset, the AHB uses SINGLE and INCR burst transfer operations.
RxDMA requests are given priority over TxDMA requests in the following ratio:
This is valid only when the DA bit is cleared.
These bits indicate the maximum number of beats to be transferred in one DMA transaction.
This is the maximum value that is used in a single block read/write operation. The DMA always
attempts to burst as specified in PBL each time it starts a burst transfer on the host bus. PBL
can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in
undefined behavior. When USP is set, this PBL value is applicable for TxDMA transactions
only.
The PBL values have the following limitations:
– The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx
– The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO.
– If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx
– Do not program out-of-range PBL values, because the system may not behave properly.
This bit specifies the number of Word/Dword/Lword (depending on 32/64/128-bit bus) to skip
between two unchained descriptors. The address skipping starts from the end of current
descriptor to the start of next descriptor. When DSL value equals zero, the descriptor table is
taken as contiguous by the DMA, in Ring mode.
When this bit is set, the MAC DMA controller resets all MAC Subsystem internal registers and
logic. It is cleared automatically after the reset operation has completed in all of the core clock
domains. Read a 0 value in this bit before re-programming any register of the core.
00: 1:1
01: 2:1
10: 3:1
11: 4:1
FIFO.
FIFO depths must be considered.
0: Round-robin with Rx:Tx priority given in bits [15:14]
1: Rx has priority over Tx
Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 9
933/995