MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 99

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
6.3.9
Note:
RTC
EN
31
15
rw
30
14
Bits 31:17
Backup domain control register (RCC_BDCR)
Address offset: 0x20
Reset value: 0x0000 0000, reset by Backup domain Reset.
Access: 0  wait state  3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
LSEON, LSEBYP, RTCSEL and RTCEN bits of the
(RCC_BDCR)
protected and the DBP bit in the
these can be modified. Refer to
only reset after a Backup domain Reset (see
internal or external Reset will not have any effect on these bits.
Bit 4 TIM6EN: Timer 6 clock enable
Bit 3 TIM5EN: Timer 5 clock enable
Bit 2 TIM4EN: Timer 4 clock enable
Bit 1 TIM3EN: Timer 3 clock enable
Bit 0 TIM2EN: Timer 2 clock enable
29
13
Reserved
Reserved, always read as 0.
Set and cleared by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled
Set and cleared by software.
0: Timer 5 clock disabled
1: Timer 5 clock enabled
Set and cleared by software.
0: Timer 4 clock disabled
1: Timer 4 clock enabled
Set and cleared by software.
0: Timer 3 clock disabled
1: Timer 3 clock enabled
Set and cleared by software.
0: Timer 2 clock disabled
1: Timer 2 clock enabled
28
12
are in the Backup domain. As a result, after Reset, these bits are write-
27
11
26
10
Low-, medium- and high-density reset and clock control (RCC)
RTCSEL[1:0]
25
rw
9
Doc ID 13902 Rev 9
Section 5 on page 66
Reserved
Power control register (PWR_CR)
24
rw
8
23
7
Section 6.1.3: Backup domain
22
6
Backup domain control register
Reserved
for further information. These bits are
21
5
20
4
has to be set before
19
3
BYP
LSE
18
rw
2
reset). Any
RDY
LSE
17
1
r
99/995
BDRST
LSEON
16
rw
rw
0