MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 329

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
●
●
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 113. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
1.
Figure 114. Counter timing diagram, internal clock divided by 2
Here, center-aligned mode 1 is used (for more details refer to
page
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
355).
Update interrupt flag (UIF)
Update interrupt flag (UIF)
TImer clock = CK_CNT
Timer clock = CK_CNT
Update event (UEV)
Update event (UEV)
Counter underflow
Counter underflow
Counter overflow
Counter register
Counter register
Doc ID 13902 Rev 9
CNT_EN
CNT_EN
CK_INT
CK_INT
04
0003
03 02 01 00 01
Section 14.4.1: TIMx control register 1 (TIMx_CR1) on
0002
0001
0000 0001 0002 0003
02
General-purpose timer (TIMx)
03 04 05 06 05 04 03
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