MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 393

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
16.4.2
15
14
Bits 15:6 Reserved, forced by hardware to 0.
RTC control register low (RTC_CRL)
Address offset: 0x04
Reset value: 0x0020
Bit 5 RTOFF: RTC operation OFF
Bit 4 CNF: Configuration flag
Bit 3 RSF: Registers synchronized flag
Bit 2 OWF: Overflow flag
Bit 1 ALRF: Alarm flag
Bit 0 SECF: Second flag
13
With this bit the RTC reports the status of the last write operation performed on its registers,
indicating if it has been completed or not. If its value is ‘0’ then it is not possible to write to
any of the RTC registers. This bit is read only.
0: Last write operation on RTC registers is still ongoing.
1: Last write operation on RTC registers terminated.
This bit must be set by software to enter in configuration mode so as to allow new values to
be written in the RTC_CNT, RTC_ALR or RTC_PRL registers. The write operation is only
executed when the CNF bit is reset by software after has been set.
0: Exit configuration mode (start update of RTC registers).
1: Enter configuration mode.
This bit is set by hardware at each time the RTC_CNT and RTC_DIV registers are updated
and cleared by software. Before any read operation after an APB1 reset or an APB1 clock
stop, this bit must be cleared by software, and the user application must wait until it is set to
be sure that the RTC_CNT, RTC_ALR or RTC_PRL registers are synchronized.
0: Registers not yet synchronized.
1: Registers synchronized.
This bit is set by hardware when the 32-bit programmable counter overflows. An interrupt is
generated if OWIE=1 in the RTC_CRH register. It can be cleared only by software. Writing
‘1’ has no effect.
0: Overflow not detected
1: 32-bit programmable counter overflow occurred.
This bit is set by hardware when the 32-bit programmable counter reaches the threshold set
in the RTC_ALR register. An interrupt is generated if ALRIE=1 in the RTC_CRH register. It
can be cleared only by software. Writing ‘1’ has no effect.
0: Alarm not detected
1: Alarm detected
This bit is set by hardware when the 32-bit programmable prescaler overflows, thus
incrementing the RTC counter. Hence this flag provides a periodic signal with a period
corresponding to the resolution programmed for the RTC counter (usually one second). An
interrupt is generated if SECIE=1 in the RTC_CRH register. It can be cleared only by
software. Writing ‘1’ has no effect.
0: Second flag condition not met.
1: Second flag condition met.
12
11
Reserved
10
9
Doc ID 13902 Rev 9
8
7
6
RTOFF
5
r
CNF
rw
4
rc_w0
RSF
Real-time clock (RTC)
3
rc_w0
OWF
2
rc_w0
ALRF
1
393/995
SECF
rc_w0
0