MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 114
MCBSTM32EXL
Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Specifications of MCBSTM32EXL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Connectivity line devices: reset and clock control (RCC)
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Bits 23:20
Bit 28 PLL3ON: PLL3 enable
Bit 27 PLL2RDY: PLL2 clock ready flag
Bit 26 PLL2ON: PLL2 enable
Bit 25 PLLRDY: PLL clock ready flag
Bit 24 PLLON: PLL enable
Bit 19 CSSON: Clock security system enable
Bit 18 HSEBYP: External high-speed clock bypass
Bit 17 HSERDY: External high-speed clock ready flag
Set and cleared by software to enable PLL3.
Cleared by hardware when entering Stop or Standby mode.
0: PLL3 OFF
1: PLL3 ON
Set by hardware to indicate that the PLL2 is locked.
0: PLL2 unlocked
1: PLL2 locked
Set and cleared by software to enable PLL2.
Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if
the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is
used as system clock).
0: PLL2 OFF
1: PLL2 ON
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock. Software
must disable the USB OTG FS clock before clearing this bit.
0: PLL OFF
1: PLL ON
Reserved, always read as 0.
Set and cleared by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 3-25 MHz oscillator is ready.
Set and cleared by software in debug for bypassing the oscillator with an external clock.
This bit can be written only if the external 3-25 MHz oscillator is disabled.
0: external 3-25 MHz oscillator not bypassed
1: external 3-25 MHz oscillator bypassed with external clock
Set by hardware to indicate that the external 3-25 MHz oscillator is stable. This bit needs 6
cycles of external 3-25 MHz oscillator clock to fall down after HSEON reset.
0: external 3-25 MHz oscillator not ready
1: external 3-25 MHz oscillator ready
Doc ID 13902 Rev 9
RM0008
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