MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 83

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
6.3.1
31
15
r
30
14
Bits 31:26
Bits 23:20
r
Bit 25 PLLRDY: PLL clock ready flag
Bit 24 PLLON: PLL enable
Bit 19 CSSON: Clock security system enable
Bit 18 HSEBYP: External high-speed clock bypass
Bit 17 HSERDY: External high-speed clock ready flag
Clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
29
13
r
Reserved
Reserved, always read as 0.
Reserved, always read as 0.
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Set and cleared by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 4-25 MHz oscillator is ready.
Set and cleared by software in debug for bypassing the oscillator with an external clock. This
bit can be written only if the external 4-25 MHz oscillator is disabled.
0: external 4-25 MHz oscillator not bypassed
1: external 4-25 MHz oscillator bypassed with external clock
Set by hardware to indicate that the external 4-25 MHz oscillator is stable. This bit needs 6
cycles of external 4-25 MHz oscillator clock to fall down after HSEON reset.
0: external 4-25 MHz oscillator not ready
1: external 4-25 MHz oscillator ready
28
12
HSICAL[7:0]
r
27
11
r
26
10
r
Low-, medium- and high-density reset and clock control (RCC)
RDY
PLL
25
9
r
r
Doc ID 13902 Rev 9
PLLON
24
rw
8
r
23
rw
7
22
rw
6
Reserved
HSITRIM[4:0]
21
rw
5
20
rw
4
CSS
ON
19
rw
rw
3
HSE
BYP
Res.
18
rw
2
HSE
RDY
RDY
HSI
17
1
r
r
83/995
HSION
HSE
ON
16
rw
rw
0