MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 631

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
●
●
The master can decide to enter Transmitter or Receiver mode depending on the LSB of the
slave address sent.
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●
Master transmitter
Following the address transmission and after clearing ADDR, the master sends bytes from
the DR register to the SDA line via the internal shift register.
The master waits until the first data byte is written into I2C_DR (see
sequencing EV8_1).
When the acknowledge pulse is received:
●
If TxE is set and a data byte was not written in the DR register before the end of the last data
transmission, BTF is set and the interface waits until BTF is cleared by a read from I2C_SR1
followed by a write to I2C_DR, stretching SCL low.
In 10-bit addressing mode, sending the header sequence causes the following event:
–
Then the master waits for a read of the SR1 register followed by a write in the DR
register with the second address byte (see
sequencing).
–
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see
In 7-bit addressing mode, one address byte is sent.
As soon as the address byte is sent,
–
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see
In 7-bit addressing mode,
–
–
In 10-bit addressing mode,
–
–
The TRA bit indicates whether the master is in Receiver or Transmitter mode.
The TxE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bits are set.
The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
To enter Transmitter mode, a master sends the slave address with LSB reset.
To enter Receiver mode, a master sends the slave address with LSB set.
To enter Transmitter mode, a master sends the header (11110xx0) and then the
slave address with LSB reset, (where xx denotes the two most significant bits of
the address).
To enter Receiver mode, a master sends the header (11110xx0) and then the
slave address with LSB reset. Then it should send a repeated Start condition
followed by the header (11110xx1), (where xx denotes the two most significant bits
of the address).
Figure 235
Figure 235
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Doc ID 13902 Rev 9
Figure 236
Figure 236
Transfer sequencing).
Transfer sequencing).
Figure 235
Inter-integrated circuit (I
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Figure 236
Figure 235
Transfer
2
C) interface
Transfer
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