MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 188

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA controller (DMA)
10.3.7
188/995
DMA request mapping
DMA1 controller
The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and
USARTx[1,2,3]) are simply logically ORed before entering DMA1, this means that only one
request must be enabled at a time. Refer to
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Figure 23. DMA1 request mapping
Table 57
request signals
lists the DMA requests for each channel.
USART3_RX
SPI/I2S2_RX
USART1_RX
USART2_RX
SPI/I2S2_TX
USART3_TX
USART1_TX
USART2_TX
TIM1_COM
TIM1_TRIG
TIM3_TRIG
TIM2_CH3
TIM4_CH1
TIM1_CH1
TIM3_CH3
TIM1_CH2
TIM3_CH4
TIM1_CH4
TIM4_CH2
TIM2_CH1
TIM4_CH3
TIM1_CH3
TIM3_CH1
TIM2_CH2
TIM2_CH4
Peripheral
I2C2_RX
TIM2_UP
TIM3_UP
TIM1_UP
TIM4_UP
SPI1_RX
I2C1_RX
SPI1_TX
I2C2_TX
I2C1_TX
ADC1
SW TRIGGER (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
SW trigger (MEM2MEM bit)
Doc ID 13902 Rev 9
HW REQUEST 6
HW request 3
HW request 4
HW request 5
HW request 2
HW request 7
HW request 1
Figure 23: DMA1 request
Channel 7 EN bit
Channel 1 EN bit
Channel 4 EN bit
Channel 6 EN bit
Channel 3 EN bit
Channel 5 EN bit
Channel 2 EN bit
Channel 1
Channel 3
Channel 4
Channel 6
Channel 7
Channel 2
Channel 5
Fixed hardware priority
High priority
Low priority
mapping.
internal
request
DMA1
RM0008