MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 390

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Real-time clock (RTC)
16.3.2
16.3.3
16.3.4
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Resetting RTC registers
All system registers are asynchronously reset by a System Reset or Power Reset, except for
RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV.
The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup
Domain reset. Refer to
Reading RTC registers
The RTC core is completely independent from the RTC APB1 interface.
Software accesses the RTC prescaler, counter and alarm values through the APB1 interface
but the associated readable registers are internally updated at each rising edge of the RTC
clock resynchronized by the RTC APB1 clock. This is also true for the RTC flags.
This means that the first read to the RTC APB1 registers may be corrupted (generally read
as 0) if the APB1 interface has previously been disabled and the read occurs immediately
after the APB1 interface is enabled but before the first internal update of the registers. This
can occur if:
●
●
●
In all the above cases, the RTC core has been kept running while the APB1 interface was
disabled (reset, not clocked or unpowered).
Consequently when reading the RTC registers, after having disabled the RTC APB1
interface, the software must first wait for the RSF bit (Register Synchronized Flag) in the
RTC_CRL register to be set by hardware.
Note that the RTC APB1 interface is not affected by WFI and WFE low-power modes.
Configuring RTC registers
To write in the RTC_PRL, RTC_CNT, RTC_ALR registers, the peripheral must enter
Configuration Mode. This is done by setting the CNF bit in the RTC_CRL register.
In addition, writing to any RTC register is only enabled if the previous write operation is
finished. To enable the software to detect this situation, the RTOFF status bit is provided in
the RTC_CR register to indicate that an update of the registers is in progress. A new value
can be written to the RTC registers only when the RTOFF status bit value is ’1’.
Configuration procedure:
1.
2.
3.
4.
5.
The write operation only executes when the CNF bit is cleared; it takes at least three
RTCCLK cycles to complete.
A system reset or power reset has occurred
The MCU has just woken up from Standby mode (see
The MCU has just woken up from Stop mode (see
Poll RTOFF, wait until its value goes to ‘1’
Set the CNF bit to enter configuration mode
Write to one or more RTC registers
Clear the CNF bit to exit configuration mode
Poll RTOFF, wait until its value goes to ‘1’ to check the end of the write operation.
Section 6.1.3 on page
Doc ID 13902 Rev 9
75.
Section 4.3: Low-power
Section 4.3: Low-power
modes)
RM0008
modes)