MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 916

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
916/995
15
14
Bits 15:10 Reserved
Bits 8:7 Reserved
Bits 4:3 Reserved
Bits 8:7 Reserved
Ethernet MAC interrupt status register (ETH_MACSR)
Address offset: 0x0038
Reset value: 0x0000 0000
The ETH_MACSR register contents identify the events in the MAC that can generate an
interrupt.
Bit 9 TSTS: Time stamp trigger status
Bit 6 MMCTS: MMC transmit status
Bit 5 MMCRS: MMC receive status
Bit 6 WFR: Wakeup frame received
Bit 5 MPR: Magic packet received
Bit 2 WFE: Wakeup frame enable
Bit 1 MPE: Magic Packet enable
Bit 0 PD: Power down
13
Reserved
This bit is set high when the system time value equals or exceeds the value specified in the
Target time high and low registers. This bit is cleared when this register is read.
This bit is set high whenever an interrupt is generated in the ETH_MMCTIR Register. This bit is
cleared when all the bits in this interrupt register (ETH_MMCTIR) are cleared.
This bit is set high whenever an interrupt is generated in the ETH_MMCRIR register. This bit is
cleared when all the bits in this interrupt register (ETH_MMCRIR) are cleared.
When set, this bit indicates the power management event was generated due to reception of a
wakeup frame. This bit is cleared by a read into this register.
When set, this bit indicates the power management event was generated by the reception of a
Magic Packet. This bit is cleared by a read into this register.
When set, this bit enables the generation of a power management event due to wakeup frame
reception.
When set, this bit enables the generation of a power management event due to Magic Packet
reception.
When this bit is set, all received frames will be dropped. This bit is cleared automatically when
a magic packet or wakeup frame is received, and Power-down mode is disabled. Frames
received after this bit is cleared are forwarded to the application. This bit must only be set
when either the Magic Packet Enable or Wakeup Frame Enable bit is set high.
12
11
10
TSTS
rc_r
9
Doc ID 13902 Rev 9
8
Reserved
7
MMCTS MMCRS MMCS
6
r
5
r
4
r
PMTS
3
r
2
Reserved
1
RM0008
0