MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 432

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Flexible static memory controller (FSMC)
Figure 173. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held
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HCLK
CLK
A[25:16]
NEx
NOE
NWE
NADV
NWAIT
(WAITCFG = 0)
NWAIT
(WAITCFG = 1)
A/D[15:0]
low.
High
Table 109. FSMC_BCRx bit fields
31-20
19
18-15
14
13
12
1 clock
cycle
Bit No.
addr[25:16]
1 clock
cycle
Addr[15:0]
CBURSTRW
EXTMOD
WAITEN
WREN
DATALAT CLK cycles
Bit name
Memory transaction = burst of 4 half words
0x0000
No effect on synchronous read
0x0
0x0
When high, the first data after latency period is taken as always
valid, regardless of the wait from memory value
no effect on synchronous read
data
Doc ID 13902 Rev 9
Data strobes
data
inserted wait state
Value to set
data
Data strobes
data
RM0008
ai14730

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