MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 497

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
20.9.1
Note:
20.9.2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:15
Bits 12:11 WIDBUS: Wide bus mode enable bit
Bits 31:2
SDIO power control register (SDIO_POWER)
Address offset: 0x00
Reset value: 0x0000 0000
After a data write, data cannot be written to this register for seven HCLK clock periods.
SDI clock control register (SDIO_CLKCR)
Address offset: 0x04
Reset value: 0x0000 0000
The SDIO_CLKCR register controls the SDIO_CK output clock.
Bit 14 HWFC_EN: HW Flow Control enable
Bit 13 NEGEDGE:SDIO_CK dephasing selection bit
[1:0] PWRCTRL: Power supply control bits.
These bits are used to define the current functional state of the card clock:
00: Power-off: the clock to card is stopped.
01: Reserved
10: Reserved power-up
11: Power-on: the card is clocked.
Reserved, always read as 0.
0b: HW Flow Control is disabled
1b: HW Flow Control is enabled
When HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt
signals, please see SDIO Status register definition in
0b: SDIO_CK generated on the rising edge of the master clock SDIOCLK
1b: SDIO_CK generated on the falling edge of the master clock SDIOCLK
00: Default bus mode: SDIO_D0 used
01: 4-wide bus mode: SDIO_D[3:0] used
10: 8-wide bus mode: SDIO_D[7:0] used
Reserved, always read as 0.
Reserved
Doc ID 13902 Rev 9
Reserved
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Secure digital input/output interface (SDIO)
WID
BUS
Section
9
9
8
8
20.9.11.
7
7
6
6
5
5
CLKDIV
4
4
3
3
2
2
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PWRC
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1
1
TRL
0
0