MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 258

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced-control timers (TIM1&TIM8)
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preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
●
●
●
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 54. Counter timing diagram, internal clock divided by 1
Figure 55. Counter timing diagram, internal clock divided by 2
The repetition counter is reloaded with the content of TIMx_RCR register,
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
Update interrupt flag (UIF)
Update interrupt flag (UIF)
Timer clock = CK_CNT
Timer clock = CK_CNT
Update event (UEV)
Update event (UEV)
Counter overflow
Counter overflow
Counter register
Counter register
Doc ID 13902 Rev 9
CK_PSC
CNT_EN
CK_PSC
CNT_EN
31
0034
32 33 34 35 36
0035
0036
0000 0001 0002 0003
00
01 02 03 04 05 06 07
RM0008