MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 641

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
24.6
24.6.1
RST
SW
15
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Res.
14
DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details,
refer to
I
Refer to
Control register 1 (I2C_CR1)
Address offset: 0x00
Reset value: 0x0000
ALERT
Bit 15 SWRST: Software reset
Bit 14 Reserved, forced by hardware to 0.
Bit 13 ALERT: SMBus alert
Bit 12 PEC: Packet error checking
Bit 11 POS: Acknowledge/PEC Position (for data reception)
2
13
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C registers
Note: This bit can be used in case the BUSY bit is set to ‘1’ when no stop condition has been
Note: PEC calculation is corrupted by an arbitration loss.
Note: The POS bit must be used only in 2-byte reception configuration and must be
PEC
Section 29.16.2: Debug support for timers, watchdog, bxCAN and I
12
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Section 1.1 on page 37
When set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are
released and the bus is free.
0: I
1: I
This bit is set and cleared by software, and cleared by hardware when PE=0.
0: Releases SMBAlert pin high. Alert Response Address Header followed by NACK.
1: Drives SMBAlert pin low. Alert Response Address Header followed by ACK.
This bit is set and cleared by software, and cleared by hardware when PEC is transferred or
by a START or Stop condition or when PE=0.
0: No PEC transfer
1: PEC transfer (in Tx or Rx mode)
This bit is set and cleared by software and cleared by hardware when PE=0.
0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The
PEC bit indicates that current byte in shift register is a PEC.
1: ACK bit controls the (N)ACK of the next byte which will be received in the shift register.
The PEC bit indicates that the next byte in the shift register is a PEC
2
2
C Peripheral not under reset
C Peripheral under reset state
detected on the bus.
configured before data reception starts.
To NACK the 2nd byte, the ACK bit must be cleared after ADDR is cleared.
To check the 2nd byte as PEC, the PEC bit must be set during the ADDR stretch event
after configuring the POS bit.
POS
11
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ACK
10
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STOP START
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9
Doc ID 13902 Rev 9
for a list of abbreviations used in register descriptions.
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8
STRETCH
NO
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7
ENGC
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6
Inter-integrated circuit (I
PEC
EN
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5
ARP
EN
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4
TYPE
SMB
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3
Res.
2
2
C on page
2
C) interface
BUS
SM
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1
641/995
972.
PE
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0