MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 936

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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Bits 31:30 Reserved
Bits 25:23 EBS: Error bits status
Bits 22:20 TPS: Transmit process state
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Bit 29 TSTS: Time stamp trigger status
Bit 28 PMTS: PMT status
Bit 27 MMCS: MMC status
Bit 26 Reserved
ETH_DMASR register[16:0] clears them and writing 0 has no effect. Each field (bits [16:0])
can be masked by masking the appropriate bit in the ETH_DMAIER register.
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This bit indicates an interrupt event in the MAC core's Time stamp generator block. The
software must read the MAC core’s status register, clearing its source (bit 9), to reset this bit to
0. When this bit is high an interrupt is generated if enabled.
This bit indicates an event in the MAC core’s PMT. The software must read the corresponding
registers in the MAC core to get the exact cause of interrupt and clear its source to reset this bit
to 0. The interrupt is generated when this bit is high if enabled.
This bit reflects an event in the MMC of the MAC core. The software must read the
corresponding registers in the MAC core to get the exact cause of interrupt and clear the
source of interrupt to make this bit as 0. The interrupt is generated when this bit is high if
enabled.
These bits indicate the type of error that caused a bus error (error response on the AHB
interface). Valid only with the fatal bus error bit (ETH_DMASR register [13]) set. This field does
not generate an interrupt.
Bit 23
Bit 24
Bit 25
These bits indicate the Transmit DMA FSM state. This field does not generate an interrupt.
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000: Stopped; Reset or Stop Transmit Command issued
001: Running; Fetching transmit transfer descriptor
010: Running; Waiting for status
011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx
FIFO)
100, 101: Reserved for future use
110: Suspended; Transmit descriptor unavailable or transmit buffer underflow
111: Running; Closing transmit descriptor
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1
0
1
0
1
0
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Error during data transfer by TxDMA
Error during data transfer by RxDMA
Error during read transfer
Error during write transfer
Error during descriptor access
Error during data buffer access
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Doc ID 13902 Rev 9
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RM0008
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