MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 126

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Connectivity line devices: reset and clock control (RCC)
7.3.7
126/995
Res.
31
15
USAR
T1EN
30
14
rw
Bits 31:15
APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
Bit 14 USART1EN: USART1 clock enable
Bit 13 Reserved, always read as 0.
Bit 12 SPI1EN: SPI 1 clock enable
Bit 4 FLITFEN: FLITF clock enable
Bit 3 Reserved, always read as 0.
Bit 2 SRAMEN: SRAM interface clock enable
Bit 1 DMA2EN: DMA2 clock enable
Bit 0 DMA1EN: DMA1 clock enable
Res.
29
13
SPI1
Reserved, always read as 0.
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Set and cleared by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled
EN
Set and cleared by software to disable/enable FLITF clock during sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode
1: SRAM interface clock enabled during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
28
12
rw
TIM1
EN
27
11
rw
ADC2
EN
26
10
rw
ADC1
EN
25
rw
9
Doc ID 13902 Rev 9
24
8
Reserved
Reserved
23
7
IOPE
EN
22
rw
6
IOPD
EN
21
rw
5
IOPC
EN
20
rw
4
IOPB
EN
19
rw
3
IOPA
EN
18
rw
2
Res.
17
1
RM0008
AFIO
EN
16
rw
0