MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 620

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial peripheral interface (SPI)
23.5.7
23.5.8
620/995
15
15
r
Bits 15:12 Reserved: Forced to 0 by hardware
Bits 15:0 TxCRC[15:0]: Tx CRC register
Bit 9:8 I2SCFG: I2S configuration mode
Bit 11 I2SMOD: I2S mode selection
Bit 10 I2SE: I2S Enable
14
14
Reserved
r
SPI Tx CRC register (SPI_TXCRCR) (not used in I
Address offset: 0x18
Reset value: 0x0000
SPI_I
Address offset: 1Ch
Reset value: 0x0000
Note: A read to this register when the BSY flag is set could return an incorrect value.
Note: This bit should be configured when the SPI or I
Note: Not used in SPI mode
Note: This bit should be configured when the I
13
13
When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the
subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to
1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register.
Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF bit of
SPI_CR1 is cleared). CRC calculation is done based on CRC8.
The entire 16-bits of this register are considered when a 16-bit data frame format is selected (DFF
bit of the SPI_CR1 register is set). CRC calculation is done based on CRC16 - CCITT standard.
0: SPI mode is selected
1: I2S mode is selected
0: I
1: I
00: Slave - transmit
01: Slave - receive
10: Master - transmit
11: Master - receive
r
2
2
S peripheral is disabled
S peripheral is enabled
2
Not used for the I
Not used for the SPI mode
S configuration register (SPI_I2SCFGR)
12
12
r
I2SMOD
11
rw
11
r
I2SE
10
rw
10
r
2
S mode.
rw
9
9
r
I2SCFG
Doc ID 13902 Rev 9
TxCRC[15:0]
rw
8
8
r
PCMSY
NC
rw
7
7
r
2
S is disabled.
Reserved
6
r
6
2
S is disabled
5
r
rw
5
I2SSTD
4
r
rw
4
2
S mode)
CKPOL
3
rw
r
3
rw
2
r
2
DATLEN
rw
1
1
r
RM0008
CHLEN
rw
0
0
r