MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 990

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision history
990/995
Table 215. Document revision history (continued)
11-Feb-2009
Date
Revision
8
Reset value corrected in
Section 11.10: Temperature sensor
Section 11.12.7: ADC watchdog high threshold register
Section 12.3.9: Triangle-wave generation
generation
Section 22.6: STM32F10xxx in Debug mode
master control register (CAN_MCR) on page
Note added to
Changes concerning the I
interface):
– In
– In
–
– In
–
–
–
– In
– Receiver mode modified in DR bit description in
– Note added to TxE and RxNE bit descriptions in
Changes in FSMC section:
– Data setup and Address hold min values corrected in
– Memory wait min value corrected in
– Bit descriptions modified in
– DATAST and ADDHLD are reserved when equal to 0x0000 in
– Bit descriptions modified in
– ATTHOLDx and ATTWAITx bit descriptions modified in
– IOHOLDx bit description modified in
sequence diagram for slave transmitter
sequence diagram for slave receiver
Master transmitter on page 631
Transfer sequence diagram for master transmitter
Figure 236: Transfer sequence diagram for master receiver
Overrun/underrun error (OVR) on page 634
Section 24.3.7: DMA requests
updated.
STOP bit and notes modified under POS bit.
register
register 1
Programmable NOR/PSRAM access
Card access
1..4 (FSMC_BTR1..4) on page
SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) on
page 438
(FSMC_BWTR1..4) on page
(FSMC_PMEM2..4)
space timing registers 2..4 (FSMC_PATT2..4)
(FSMC_PIO4)
Slave transmitter on page
Slave receiver on page
Closing the communication on page
Section 24.6.1: Control register 1
Doc ID 13902 Rev 9
(I2C_DR).
updated.
(I2C_SR1).
and
Section 23.3.6: CRC
parameters.
SRAM/NOR-Flash write timing registers 1..4
Section 3.4.1: Data register
2
C peripheral
629: text changes and
SRAM/NOR-Flash chip-select timing registers
Common memory space timing register 2..4
628: text changes and
440.
and
Changes
438.
and
modified. Reset value corrected in
calculation.
Section 24.3.8: Packet error checking
Table 113: Programmable NAND/PC
Master receiver on page 632
(I2C_CR1): note modified under
I/O space timing register 4
modified.
parameters.
(Inter-integrated circuit (I
632: text changes and
and
modified.
added. Bit 16 updated in
562.
Figure 49: DAC triangle wave
clarified.
Section 24.6.5: Data
Section 24.6.6: Status
Figure 234: Transfer
modified.
(CRC_DR).
Figure 233: Transfer
(ADC_HTR).
Table 88:
Attribute memory
modified.
Figure 235:
2
C)
RM0008
clarified.
CAN